Semiconductor Devices and Methods of Manufacture

ABSTRACT

Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.

PRIORITY CLAIM AND CROSS-REFERENCE

This application is a continuation of U.S. patent application Ser. No.16/930,702, filed on Jul. 16, 2020, entitled “Semiconductor Devices andMethods of Manufacture,” which claims the benefit of U.S. ProvisionalApplication No. 62/964,375, filed on Jan. 22, 2020, which applicationsare hereby incorporated herein by reference.

BACKGROUND

Electrical signaling and processing have been the mainstream techniquesfor signal transmission and processing. Optical signaling and processinghave been used in increasingly more applications in recent years,particularly due to the use of optical fiber-related applications forsignal transmission.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIGS. 1A-1B illustrates placement of a first photonic integratedcircuit, in accordance with some embodiments.

FIG. 2 illustrates a formation of a first redistribution structure, inaccordance with some embodiments.

FIG. 3 illustrates a transfer of the structure to a second carriersubstrate, in accordance with some embodiments.

FIG. 4 illustrates a formation of a second redistribution structure, inaccordance with some embodiments.

FIG. 5 illustrates a formation of external contacts, in accordance withsome embodiments.

FIG. 6 illustrates a bonding of an electronic integrated circuit, inaccordance with some embodiments.

FIG. 7 illustrates a placement of a first underfill, in accordance withsome embodiments.

FIG. 8 illustrates a singulation process, in accordance with someembodiments.

FIG. 9 illustrates a placement of an optical fiber, in accordance withsome embodiments.

FIGS. 10A-10B illustrates an encapsulation of the first photonicintegrated circuit with semiconductor dies, in accordance with someembodiments.

FIG. 11A-11B illustrates formation of a second waveguide, in accordancewith some embodiments.

FIG. 12 illustrates attachment of the structure to a second carriersubstrate, in accordance with some embodiments.

FIG. 13 illustrates formation of a second redistribution structure, inaccordance with some embodiments.

FIG. 14 illustrates formation of external contacts, in accordance withsome embodiments.

FIG. 15 illustrates bonding of the electronic integrated circuit, inaccordance with some embodiments.

FIG. 16 illustrates placement of the optical fiber, in accordance withsome embodiments.

FIG. 17 illustrates an encapsulation of the first photonic integratedcircuit with the electronic integrated circuit, in accordance with someembodiments.

FIG. 18 illustrates a first hard mask, in accordance with someembodiments.

FIG. 19 illustrates formation of an opening, in accordance with someembodiments.

FIG. 20 illustrates a thinning process, in accordance with someembodiments.

FIG. 21 illustrates formation of a second waveguide and firstredistribution structure, in accordance with some embodiments.

FIG. 22 illustrates a fully integrated device, in accordance with someembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the invention. Specificexamples of components and arrangements are described below to simplifythe present disclosure. These are, of course, merely examples and arenot intended to be limiting. For example, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed between the first and second features, such thatthe first and second features may not be in direct contact. In addition,the present disclosure may repeat reference numerals and/or letters inthe various examples. This repetition is for the purpose of simplicityand clarity and does not in itself dictate a relationship between thevarious embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

Embodiments will now be described with respect to specific methods andprocesses which work to protect sensitive components of photonicintegrated circuits such as grating couplers and waveguides. However,the embodiments discussed herein are intended to be representative andare not meant to limit the embodiments in any fashion.

With reference now to FIGS. 1A-1B, with FIG. 1B being a close-up view ofthe dashed box labeled 110 in FIG. 1A, there is illustrated a method offorming a pluggable modularized device which comprises a first carriersubstrate 101, an first adhesive layer 103 over the first carriersubstrate 101, and the formation of through insulator vias (TIVs) 107over the first adhesive layer 103. The first carrier substrate 101comprises, for example, silicon based materials, such as glass orsilicon oxide, or other materials, such as aluminum oxide, combinationsof any of these materials, or the like. The first carrier substrate 101is planar in order to accommodate an attachment of semiconductor devicessuch as a first photonic integrated circuit 105 (described furtherbelow).

The first adhesive layer 103 is placed on the first carrier substrate101 in order to assist in the adherence of overlying structures (e.g.,the first photonic integrated circuit 105). In an embodiment the firstadhesive layer 103 may comprise a die attach film, an ultra-violet glue,which loses its adhesive properties when exposed to ultra-violet light.However, other types of adhesives, such as pressure sensitive adhesives,radiation curable adhesives, epoxies, combinations of these, or thelike, may also be used. The first adhesive layer 103 may be placed ontothe first carrier substrate 101 in a semi-liquid or gel form, which isreadily deformable under pressure.

The TIVs 107 are formed over the first adhesive layer 103, and comprisea first seed layer (not shown separately from the TIVs 107). The firstseed layer is formed over the first adhesive layer 103, and is a thinlayer of a conductive material that aids in the formation of a thickerlayer during subsequent processing steps. The first seed layer maycomprise a layer of titanium about 1,000 Å thick followed by a layer ofcopper about 5,000 Å thick. The first seed layer may be created usingprocesses such as sputtering, evaporation, or PECVD processes, dependingupon the desired materials. The first seed layer may be formed to have athickness of between about 0.3 μm and about 1 μm, such as about 0.5 μm.

Once the first seed layer has been formed, a photoresist (not separatelyillustrated) is placed and patterned over the first seed layer. In anembodiment the photoresist may be placed on the first seed layer using,e.g., a spin coating technique to a height of between about 50 μm andabout 250 μm, such as about 120 μm. Once in place, the photoresist maythen be patterned by exposing the photoresist to a patterned energysource (e.g., a patterned light source) so as to induce a chemicalreaction, thereby inducing a physical change in those portions of thephotoresist exposed to the patterned light source. A developer is thenapplied to the exposed photoresist to take advantage of the physicalchanges and selectively remove either the exposed portion of thephotoresist or the unexposed portion of the photoresist, depending uponthe desired pattern.

In an embodiment the pattern formed into the photoresist is a patternfor the TIVs 107. The TIVs 107 are formed in such a placement as toallow electrical paths to be located adjacent to the subsequently placedfirst photonic integrated circuit 105 and may be formed with a pitch ofless than about 40 μm. However, any suitable arrangement for the patternof TIVs 107, such as by being located such that one or more firstphotonic integrated circuits 105 are placed on opposing sides of theTIVs 107, may be utilized.

In an embodiment the TIVs 107 are formed within the photoresist andcomprise one or more conductive materials, such as copper, tungsten,other conductive metals, or the like. The TIVs 107 may be formed, forexample, by electroplating, electroless plating, or the like. In anembodiment, an electroplating process is used wherein the first seedlayer and the photoresist are submerged or immersed in an electroplatingsolution. The first seed layer surface is electrically connected to thenegative side of an external DC power supply such that the first seedlayer functions as the cathode in the electroplating process. A solidconductive anode, such as a copper anode, is also immersed in thesolution and is attached to the positive side of the power supply. Theatoms from the anode are dissolved into the solution, from which thecathode, e.g., the first seed layer, acquires the dissolved atoms,thereby plating the exposed conductive areas of the first seed layerwithin the opening of the photoresist.

Once the TIVs 107 have been formed using the photoresist and the firstseed layer, the photoresist may be removed using a suitable removalprocess. In an embodiment, a plasma ashing process may be used to removethe photoresist, whereby the temperature of the photoresist may beincreased until the photoresist experiences a thermal decomposition andmay be removed. However, any other suitable process, such as a wetstrip, may be utilized. The removal of the photoresist may expose theunderlying portions of the first seed layer.

Once exposed a removal of the exposed portions of the first seed layermay be performed. In an embodiment the exposed portions of the firstseed layer (e.g., those portions that are not covered by the TIVs 107)may be removed by, for example, a wet or dry etching process. Forexample, in a dry etching process reactants may be directed towards thefirst seed layer using the TIVs 107 as masks. In another embodiment,etchants may be sprayed or otherwise put into contact with the firstseed layer in order to remove the exposed portions of the first seedlayer. After the exposed portion of the first seed layer has been etchedaway, a portion of the first adhesive layer 103 is exposed between theTIVs 107.

FIG. 1A additionally illustrates a placement of the first photonicintegrated circuit 105 onto the first adhesive layer 103. The firstphotonic integrated circuit 105 is utilized to transmit and receiveoptical signals. In particular, the first photonic integrated circuit105 converts electrical signals to optical signals for transmissionalong an optical fiber 901 (not illustrated in FIGS. 1A-1B, butillustrated and described further below with respect to FIG. 9 ), andconvert optical signals from the optical fiber 901 to electricalsignals. Accordingly, the first photonic integrated circuit 105 isresponsible for the input/output (I/O) of optical signals to/from theoptical fiber 901.

FIG. 1B illustrates a close up view of the dashed box 110 in FIG. 1A andshows a close up, more detailed view of the first photonic integratedcircuit 105. In an embodiment the first photonic integrated circuit 105may be formed using a silicon-on-insulator (SoI) substrate 151.Generally, an SOI substrate comprises a layer of a semiconductormaterial 153, such as silicon, formed on an insulator layer 155. Theinsulator layer 155 may be, for example, a buried oxide (BOX) layer or asilicon oxide layer. The insulator layer 155 is provided on a substrate158, typically a silicon or glass substrate. Other substrates, such as amulti-layered or gradient substrate may also be used.

FIG. 1B additionally illustrates formation of a grating coupler 157 overwaveguides 154 formed within the semiconductor material 153. In anembodiment the waveguides 154 may be silicon waveguides formed bypatterning the semiconductor material 153. Patterning the semiconductormaterial 153 may be accomplished with acceptable photolithography andetching techniques. For example, a photoresist may be formed anddeveloped on the front side of the semiconductor material 153. Thephotoresist may be patterned with openings corresponding to thewaveguides 154. One or more etching processes may be performed using thepatterned photoresist as an etching mask. In particular, the front sideof the semiconductor material 153 may be etched to form recessesdefining the waveguides 154; the remaining unrecessed portions of thesemiconductor material 153 form the waveguides 154, with sidewalls ofthe remaining unrecessed portions defining sidewalls of the waveguides154. The etching processes may be an anisotropic wet or dry etch. Itshould be appreciated that the dimensions of the waveguides 154 dependson the application; in an embodiment, the waveguides 154 have a width offrom about 500 nm to about 3000 nm, such as about 500 nm, and a heightof from about 220 nm to about 300 nm, such as about 250 nm.

The waveguides 154 further comprise the grating couplers 157, which areformed in top portions of the waveguides 154. The grating couplers 157allow the waveguides 154 to transmit light to or receive light from anoverlying light source or optical signal source (e.g., the optical fiber901). The grating couplers 157 may be formed by acceptablephotolithography and etching techniques. In an embodiment, the gratingcouplers 157 are formed after the waveguides 154 are defined. Forexample, a photoresist may be formed and developed on the front side ofthe semiconductor material 153 (e.g., on the waveguides 154 and in therecesses defining them). The photoresist may be patterned with openingscorresponding to the grating couplers 157, and one or more etchingprocesses may be performed using the patterned photoresist as an etchingmask. In particular, the front side of the semiconductor material 153may be etched to form recesses in the waveguides 154 defining thegrating couplers 157. The etching processes may be an anisotropic wet ordry etch.

Once the waveguides 154 and the grating coupler 157 have been formed, adielectric layer 159 is formed on the front side of the semiconductormaterial 153. The dielectric layer 159 is formed over the waveguides 154and the grating coupler 157, and in the recesses defining the waveguides154 and grating couplers 157. The dielectric layer 159 may be formed ofsilicon oxide, silicon nitride, a combination thereof, or the like, andmay be formed by CVD, PVD, atomic layer deposition (ALD), aspin-on-dielectric process, the like, or a combination thereof. Afterformation, the dielectric layer 159 may be planarized, such as by achemical mechanical polish (CMP) or a mechanical grinding, to avoidtransfer of the pattern of the waveguides 154 to the dielectric layer159. In an embodiment, the dielectric layer 159 is an oxide of thematerial of the semiconductor material 153, such as silicon oxide. Dueto the difference in refractive indices of the materials of thewaveguides 154 and dielectric layer 159, the waveguides 154 have highinternal reflections such that light is confined in the waveguides 154,depending on the wavelength of the light and the reflective indices ofthe respective materials. In an embodiment, the refractive index of thematerial of the waveguides 154 is higher than the refractive index ofthe material of the dielectric layer 159.

FIG. 1B additionally illustrates a formation of a redistributionstructure 161, such as a back end of line (BEOL) structure over thesemiconductor material 153 and the dielectric layer 159 in order to makeelectrical connections to the structures within the first photonicintegrated circuit 105. In an embodiment the redistribution structure161 may be formed of one or more layers of conductive materialsseparated by one or more layers of dielectric materials. In someembodiments, the dielectric material is deposited and then patterned inorder to form openings, and then those openings are filled and/oroverfilled with a conductive material. The conductive material is thenplanarized in order to embed the conductive material into the dielectricmaterial in either a damascene or dual damascene process. Once a firstlevel has been formed, additional levels may be formed by repeating thedamascene or dual damascene processes.

Once the redistribution structure 161 has been formed, contact pads 162(see FIG. 1A) may be formed over the redistribution structure 161 inorder to provide electrical connectivity between the redistributionstructure 161 and overlying structures. In an embodiment the contactpads 162 are formed of a conductive material such as aluminum, althoughother suitable materials, such as copper, tungsten, or the like, mayalternatively be utilized. The contact pads 162 may be formed using aprocess such as CVD, although other suitable materials and methods mayalternatively be utilized. Once the material for the contact pads 162has been deposited, the material may be shaped into the contact pads 162using, e.g., a photolithographic masking and etching process.

A passivation film 163 is formed on the back side of the redistributionstructure 161. The passivation film 163 may be formed from one or moredielectric materials, such as silicon oxide, silicon nitride, the like,or combinations thereof, using a deposition process such as chemicalvapor deposition, physical vapor deposition, atomic layer deposition,combinations of these, or the like. In a particular embodiment thepassivation film 163 may be a tri-layer film which comprises two layersof dielectric materials which sandwich a layer of a conductive material,such as a a metal like aluminum. However, any suitable material andmethod of manufacture may be utilized.

Once the passivation film 163 has been formed, a protection layer 165may be formed over the passivation film 163. In an embodiment theprotection layer 165 may be a polymer based dielectric material such aspolyimide, although any suitable material, such as polybenzoxazole (PBO)or a polyimide derivative, may be utilized. The protection layer 165 maybe placed using, e.g., a spin-coating process. However, any suitablematerial and method of deposition may be used.

After the protection layer 165 has been formed, external contacts 164(see FIG. 1A) may be formed to provide external connection to the firstphotonic integrated circuit 105. In an embodiment the external contacts164 may be conductive pillars such as copper pillars and may be formedby initially patterning the protection layer 165 and the passivationfilm 163 to expose portions of the underlying contact pads 162 using,e.g., a photolithographic masking with a photoresist and etchingprocess. Once the contact pads 162 have been exposed, conductivematerial may be plated into the openings through the photoresist and theprotection layer 165, and the photoresist may be removed. The externalcontacts 164 may be formed with a pitch of greater than about 25 μm.However, any suitable materials, methods, and pitches may be utilized.

After the external contacts 164 have been formed, the protection layer165, the passivation film 163, the redistribution structure 161, and aportion of the dielectric layer 159 are patterned to form an opening 171in order to allow the transmission of light through these layers and tothe grating coupler 157. In an embodiment the opening 171 may be formedusing a photolithographic masking and etching process whereby aphotoresist is placed over the protection layer 165, exposed, anddeveloped in order to expose the portion of the protection layer 165that is desired to be removed. Then, one or more anisotropic etchingprocesses are utilized to sequentially etch through the remaininglayers.

In an embodiment the opening 171 is sized in order to allow for thepassage of optical signals to and from the optical fiber 901. In anembodiment the opening 171 may have a first width W₁ at a top of theopening 171 of between about 30 μm and about 40 μm, and may have asecond width W₂ at a bottom of the opening 171 of between about 20 μmand about 30 μm. Additionally, the opening 171 may have a first heightH₁ no greater than about 13.5 μm, and may extend into the firstdielectric layer 159 a first depth D₁ of less than about 310 nm.However, any suitable dimensions may be utilized.

Once the opening 171 has been formed, the opening 171 may be filledusing a fill material 173. In an embodiment the fill material 173 may bea material which i s translucent to the passage of light but stillprotects the underlying structures such as the grating coupler 157 andthe waveguides 154. In particular embodiments the fill material 173 maybe a material such as polyimide, epoxy, siloxane, combinations of these,or the like. The fill material 173 may be applied or deposited using adeposition process such as spin-on, chemical vapor deposition, physicalvapor deposition, atomic layer deposition, or the like. The fillmaterial 173 may be applied or deposited to fill and overfill theopening 171 and may be deposited to a second depth over the protectionlayer 165 of between about 13 μm and about 31 μm. However, any suitablematerials, methods of formation, and thicknesses may be utilized.

Once the first photonic integrated circuit 105 has been manufactured,the first photonic integrated circuit 105 may be singulated inpreparation for placement. In an embodiment the singulation may beperformed by using a saw blade (not separately illustrated) to slicethrough the insulator SoI substrate 151 and overlying structures.However, as one of ordinary skill in the art will recognize, utilizing asaw blade for the singulation is merely one illustrative embodiment andis not intended to be limiting. Any method for performing thesingulation, such as utilizing one or more etches, may be utilized.These methods and any other suitable methods may be utilized tosingulate the structure.

Once singulated, the first photonic integrated circuit 105 is placed onthe first carrier substrate 101. In an embodiment the first photonicintegrated circuit 105 may be placed onto the first adhesive layer 103using, e.g., a pick and place process. However, any other method ofplacing the first photonic integrated circuit 105 may be used.

Returning now to FIG. 1A, FIG. 1A also illustrates an encapsulation ofthe TIVs 107 and the first photonic integrated circuit 105. Theencapsulation may be performed in a molding device (not individuallyillustrated in FIG. 1A), which may comprise a top molding portion and abottom molding portion separable from the top molding portion. When thetop molding portion is lowered to be adjacent to the bottom moldingportion, a molding cavity may be formed for the first carrier substrate101, the TIVs 107, and the first photonic integrated circuit 105.

During the encapsulation process the top molding portion may be placedadjacent to the bottom molding portion, thereby enclosing the firstcarrier substrate 101, the TIVs 107, and the first photonic integratedcircuit 105 within the molding cavity. Once enclosed, the top moldingportion and the bottom molding portion may form an airtight seal inorder to control the influx and outflux of gasses from the moldingcavity. Once sealed, an encapsulant 109 may be placed within the moldingcavity. The encapsulant 109 may be a molding compound resin such aspolyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinationsof these, or the like. The encapsulant 109 may be placed within themolding cavity prior to the alignment of the top molding portion and thebottom molding portion, or else may be injected into the molding cavitythrough an injection port.

Once the encapsulant 109 has been placed into the molding cavity suchthat the encapsulant 109 encapsulates the first carrier substrate 101,the TIVs 107, and the first photonic integrated circuit 105, theencapsulant 109 may be cured in order to harden the encapsulant 109 foroptimum protection. While the exact curing process is dependent at leastin part on the particular material chosen for the encapsulant 109, in anembodiment in which molding compound is chosen as the encapsulant 109,the curing could occur through a process such as heating the encapsulant109 to between about 100° C. and about 130° C., such as about 125° C.for about 60 sec to about 3000 sec, such as about 600 sec. Additionally,initiators and/or catalysts may be included within the encapsulant 109to better control the curing process.

However, as one having ordinary skill in the art will recognize, thecuring process described above is merely an exemplary process and is notmeant to limit the current embodiments. Other curing processes, such asirradiation or even allowing the encapsulant 109 to harden at ambienttemperature, may be used. Any suitable curing process may be used, andall such processes are fully intended to be included within the scope ofthe embodiments discussed herein.

FIG. 2 illustrates a thinning of the encapsulant 109 in order to exposethe TIVs 107 and the external contacts 164 of the first photonicintegrated circuit 105 for further processing. The thinning may beperformed, e.g., using a mechanical grinding or chemical mechanicalpolishing (CMP) process whereby chemical etchants and abrasives areutilized to react and grind away the encapsulant 109 and the fillmaterial 173 until the TIVs 107 and the external contacts 164 of thefirst photonic integrated circuit 105 have been exposed. As such, thefirst photonic integrated circuit 105 and the TIVs 107 may have a planarsurface that is also coplanar with the encapsulant 109.

However, while the CMP process described above is presented as oneillustrative embodiment, it is not intended to be limiting to theembodiments. Any other suitable removal process may be used to thin theencapsulant 109 and the fill material 173 and expose the TIVs 107. Forexample, a series of chemical etches may be utilized. This process andany other suitable process may be utilized to thin the encapsulant 109and the fill material 173, and all such processes are fully intended tobe included within the scope of the embodiments.

FIG. 2 additionally illustrates a formation of a first redistributionstructure 201 with a first redistribution layer 205 extending through afirst dielectric layer 203. In an embodiment the first dielectric layer203 may be a polymer based dielectric material such as polybenzoxazole(PBO), although any suitable material, such as polyimide or a polyimidederivative, may be utilized. The first dielectric layer 203 may beplaced using, e.g., a spin-coating process to a thickness of betweenabout 5 μm and about 25 μm, such as about 7 μm, although any suitablemethod and thickness may be used.

Once the first dielectric layer 203 has been placed, the firstdielectric layer 203 may be patterned in order to expose conductiveportions of the underlying structures (e.g., the TIVs 107 and theexternal contacts 164). In an embodiment the first dielectric layer 203may be patterned using, e.g., a photolithographic masking and etchingprocess, whereby a photoresist is placed, exposed, and developed, andthe photoresist is then used as a mask during an anisotropic etchingprocess. However, any suitable process for patterning the firstdielectric layer 203 may be utilized.

Once the first dielectric layer 203 has been patterned, the firstredistribution layer 205 may be formed to make contact with theunderlying conductive regions. In an embodiment the first redistributionlayer 205 may be formed by initially forming a second seed layer of atitanium copper alloy through a suitable formation process such as CVDor sputtering. Once the second seed layer has been deposited, aphotoresist (not separately illustrated) may be placed onto the secondseed layer to prepare for a formation of the first redistributionstructure 201. Once the photoresist has been formed and patterned, aconductive material, such as copper, may be formed on the second seedlayer through a deposition process such as plating. The conductivematerial may be formed to have a thickness of between about 1 μm andabout 10 μm, such as about 5 μm. However, while the material and methodsdiscussed are suitable to form the conductive material, these materialsare merely exemplary. Any other suitable materials, such as AlCu or Au,and any other suitable processes of formation, such as CVD or PVD, maybe used to form the first redistribution layer 205.

Once the conductive material has been formed, the photoresist may beremoved through a suitable removal process such as ashing, wet etching,or plasma etching. Additionally, after the removal of the photoresist,those portions of the second seed layer that were covered by thephotoresist may be removed through, for example, a suitable etch processusing the conductive material as a mask.

Once the first redistribution layer 205 has been formed, a seconddielectric layer 207 is formed over the first redistribution layer 205.In an embodiment the second dielectric layer 207 may be similar to thefirst dielectric layer 203, such as by being a polymer based dielectricformed through spin-coating. However, any suitable material and methodof deposition may be utilized.

Once the second dielectric layer 207 has been placed, the seconddielectric layer 207 may be patterned in order to expose conductiveportions of the underlying structures (e.g., the first redistributionlayer 205). In an embodiment the second dielectric layer 207 may bepatterned using, e.g., a photolithographic masking and etching process,whereby a photoresist is placed, exposed, and developed, and thephotoresist is then used as a mask during an anisotropic etchingprocess. However, any suitable process for patterning the seconddielectric layer 207 may be utilized.

In a particular embodiment the first redistribution structure 201 may beformed such that the first redistribution structure 201 has a reducedpitch between conductive elements. For example, the conductive elementsmay be formed to have a pitch of between about 4 μm and about 20 μm.However, any suitable pitch may be utilized.

Additionally, once the second dielectric layer 207 has been patterned,contact pads 209 may be formed within the openings of the seconddielectric layer 207. In an embodiment the contact pads 209 may comprisealuminum, but other materials, such as copper, may be used. The contactpads 209 may be formed using a deposition process, such as sputtering,to form a layer of material (not shown) that fills the openings withinthe second dielectric layer 207. Once filled, the material may beplanarized with the second dielectric layer 207 using, for example, achemical mechanical polishing process. However, any other suitableprocess may be utilized to form the contact pads 209.

FIG. 3 illustrates a transfer of the structure to a second carriersubstrate 301 and a removal of the first carrier substrate 101. In anembodiment the second dielectric layer 207 and the contact pads 209 maybe attached to the second carrier substrate 301 using, e.g., a secondadhesive layer 303. The second carrier substrate 301 and the secondadhesive layer 303 may be similar to the first carrier substrate 101 andthe first adhesive layer 103 (described above with respect to FIG. 1A),although any suitable structures and any suitable adhesives may beutilized.

Additionally, once the structure has been transferred to the secondcarrier substrate 301, the first carrier substrate 101 may be removed.In an embodiment the first carrier substrate 101 may be debonded using,e.g., a thermal process to alter the adhesive properties of the firstadhesive layer 103. In a particular embodiment an energy source such asan ultraviolet (UV) laser, a carbon dioxide (CO₂) laser, or an infrared(IR) laser, is utilized to irradiate and heat the first adhesive layer103 until the first adhesive layer 103 loses at least some of itsadhesive properties. Once performed, the first carrier substrate 101 andthe first adhesive layer 103 may be physically separated and removedfrom the structure.

Once attached to the second carrier substrate 301, the first photonicintegrated circuit 105, the encapsulant 109, and the TIVs 107 may bethinned in order to reduce the overall height of the structure. In anembodiment the thinning may be performed using, e.g., a chemicalmechanical polishing process. However, any suitable thinning process,such as mechanical grinding or etching processes, may be utilized.

FIG. 4 illustrates that, once the structure has been thinned, a secondredistribution structure 401 may be formed on an opposite side of thefirst photonic integrated circuit 105 from the first redistributionstructure 201 and formed in electrical connection with the TIVs 107. Inan embodiment the second redistribution structure 401 may be formedusing a series of alternating redistribution layers and dielectriclayers. Each of the dielectric layers may be a similar material formedusing similar processes as the first dielectric layer 203 (describedabove with respect to FIG. 2 ) while each of the redistribution layersmay be a similar material formed using similar processes as the firstredistribution layer 205 (also described above with respect to FIG. 2 ).However, any suitable materials and methods of manufacture may beutilized.

In an embodiment the second redistribution structure 401 may comprisethree redistribution layers and four dielectric layers. However, thisnumber is intended to be illustrative and is not intended to limiting tothe embodiments. Rather, any suitable number of redistribution layersand dielectric layers may be utilized, and all such layers are fullyintended to be included within the scope of the embodiments.

Additionally, in a particular embodiment the second redistributionstructure 401 may be formed such that the second redistributionstructure 401 has a reduced pitch between conductive elements. Forexample, the conductive elements may be formed to have a pitch ofbetween about 4 μm and about 20 μm. However, any suitable pitch may beutilized.

FIG. 5 illustrates a formation of underbump metallizations (UBM) 501 inconnection with the second redistribution structure 401. In anembodiment the formation of the UBMs 501 may be initiated by firstexposing one of the redistribution layers in the second redistributionstructure 401 using, e.g., a photolithographic masking and etchingprocess. However, any suitable patterning process may be utilized.

Once exposed, the UBMs 501 may be formed. In an embodiment the UBMs 501may comprise three layers of conductive materials, such as a layer oftitanium, a layer of copper, and a layer of nickel. However, one ofordinary skill in the art will recognize that there are many suitablearrangements of materials and layers, such as an arrangement ofchrome/chrome-copper alloy/copper/gold, an arrangement oftitanium/titanium tungsten/copper, or an arrangement ofcopper/nickel/gold, that are suitable for the formation of the UBMs 501.Any suitable materials or layers of material that may be used for theUBMs 501 are fully intended to be included within the scope of theembodiments.

In an embodiment the UBMs 501 are created by forming each layer over thesecond redistribution structure 401. The forming of each layer may beperformed using a plating process, such as electrochemical plating,although other processes of formation, such as sputtering, evaporation,or PECVD process, may also be used depending upon the desired materials.The UBMs 501 may be formed to have a thickness of between about 0.7 μmand about 10 μm, such as about 5 μm.

FIG. 5 additionally illustrates the formation of first external contacts503 on the UBMs 501. In an embodiment the first external contacts 503may be, for example, contact bumps as part of a ball grid array (BGA),although any suitable connection may be utilized. In an embodiment inwhich the first external contacts 503 are contact bumps, the firstexternal contacts 503 may comprise a material such as tin, or othersuitable materials, such as silver, lead-free tin, or copper. In anembodiment in which the first external contacts 503 are tin solderbumps, the first external contacts 503 may be formed by initiallyforming a layer of tin through such methods such as evaporation,electroplating, printing, solder transfer, ball placement, etc, to athickness of, e.g., about 250 μm. Once a layer of tin has been formed onthe structure, a reflow may be performed in order to shape the materialinto the desired bump shape.

FIG. 6 illustrates that, once the first external contacts 503 have beenformed, the first external contacts 503 may be attached to a ringstructure 601. The ring structure 601 may be a metal ring intended toprovide support and stability for the structure during and after adebonding process. In an embodiment the first external contacts 503 areattached to the ring structure using, e.g., a ultraviolet tape 603,although any other suitable adhesive or attachment may alternatively beused.

Once the first external contacts 503 and are attached to the ringstructure 601, the second carrier substrate 301 may be debonded from thestructure using, e.g., a thermal process to alter the adhesiveproperties of the second adhesive layer 303. In a particular embodimentan energy source such as an ultraviolet (UV) laser, a carbon dioxide(CO₂) laser, or an infrared (IR) laser, is utilized to irradiate andheat the second adhesive layer 303 until the second adhesive layer 303loses at least some of its adhesive properties. Once performed, thesecond carrier substrate 301 and the second adhesive layer 303 may bephysically separated and removed.

FIG. 6 additionally illustrates the placement of second externalconnectors 607 in connection with the first redistribution structure201. In an embodiment the second external connectors 607 may be contactbumps such as microbumps or controlled collapse chip connection (C4)bumps and may comprise a material such as tin, or other suitablematerials, such as solder on past, silver, or copper. In an embodimentin which the second external connectors 607 are tin solder bumps, thesecond external connectors 607 may be formed by initially forming alayer of tin through any suitable method such as evaporation,electroplating, printing, solder transfer, ball placement, etc, to athickness of, e.g., about 100 μm. Once a layer of tin has been formed onthe structure, a reflow is performed in order to shape the material intothe desired bump shape.

Once the second external connectors 607 have been formed, a firstelectronic integrated circuit (EIC) 605 may be placed into contact withthe second external connectors 607 and in electrical contact with thefirst photonic integrated circuit 105. In an embodiment the firstelectronic integrated circuit 605 may be comprise devices formed at asurface of an EIC substrate 609 (such as a silicon substrate), that areutilized to interface the first photonic integrated circuit 105 withother devices. For example, the first electronic integrated circuit 605may comprise controllers, CMOS drivers, transimpedance amplifiers, andthe like in order to perform functions such as controllinghigh-frequency signaling of the first photonic integrated circuit 105according to electrical signals (digital or analog) received from, e.g.,separate logic dies.

In an embodiment the first electronic integrated circuit 605 may furthercomprise EIC contact pads 611, an EIC passivation layer 613, a EICprotection layer 615, and EIC external contact 617. In an embodiment theEIC contact pads 611, the EIC passivation layer 613, the EIC protectionlayer 615, and the EIC external contact 617 may be similar to thecontact pads 162, the passivation film 163, the protection layer 165,and the external contacts 164, described above with respect to FIG. 1A.However, any suitable structures may be utilized.

The first electronic integrated circuit 605 may be placed onto thesecond external connectors 607 using, e.g., a pick and place process.However, any other method of placing the first electronic integratedcircuit 605 may be used. Once in physical contact, a bonding process maybe performed in order to bond the first electronic integrated circuit605 with the second external connectors 607. For example, in anembodiment in which the second external connectors 607 are solder bumps,the bonding process may comprise a reflow process whereby thetemperature of the second external connectors 607 is raised to a pointwhere the second external connectors 607 will liquefy and flow, therebybonding the first electronic integrated circuit 605 to the secondexternal connectors 607 once the second external connectors 607resolidifies.

FIG. 7 illustrates a placement of a first underfill 701 between thefirst electronic integrated circuit 605 and the first redistributionstructure 201. In an embodiment the first underfill 701 is a protectivematerial used to cushion and support the first electronic integratedcircuit 605 and the first redistribution structure 201 from operationaland environmental degradation, such as stresses caused by the generationof heat during operation. The first underfill 701 may be injected orotherwise formed in the space between the first electronic integratedcircuit 605 and the first redistribution structure 201 and may, forexample, comprise a liquid epoxy that is dispensed between the firstelectronic integrated circuit 605 and the first redistribution structure201 and then cured to harden.

FIG. 8 illustrates a singulation process used to singulate thestructure. In an embodiment the singulation may be performed by using asaw blade (represented in FIG. 8 by the dashed boxes labeled 801) toslice through the first underfill 701 and the encapsulant 109. However,as one of ordinary skill in the art will recognize, utilizing a sawblade for the singulation is merely one illustrative embodiment and isnot intended to be limiting. Any method for performing the singulation,such as utilizing one or more etches, may be utilized. These methods andany other suitable methods may be utilized to singulate the structure.

FIG. 9 illustrates an attachment of an optical fiber 901 which isutilized as an optical input/output port to the first photonicintegrated circuit 105. In an embodiment the optical fiber 901 is placedso as to optically couple the optical fiber 901 and the grating coupler157, such as by positioning the optical fiber 901 so that opticalsignals leaving the optical fiber 901 is directed through the fillmaterial 173 and hits the grating coupler 157. Similarly, the opticalfiber 901 is positioned so that optical signals leaving the gratingcoupler 157 is directed into the optical fiber 901 for transmission. Ina particular embodiment the optical fiber 901 is positioned so that theoptical fiber is located on an opposite side of the fill material 173and the first redistribution structure 201 from the grating coupler 157.However, any suitable location may be utiliz

If desired, a trench may be formed within the first redistributionstructure 201 to assist in the placement of the optical fiber 901. In anembodiment the trench may be formed within the second redistributionstructure at any point during the manufacturing process using, forexample, a photolithographic masking and etching process. However, anysuitable method or combination of methods may be utilized.

FIG. 9 further illustrates an optional bonding of the first externalcontacts 503 to another substrate 903. In an embodiment the substrate903 may be a printed circuit board such as a laminate substrate formedas a stack of multiple thin layers (or laminates) of a polymer materialsuch as bismaleimide triazine (BT), FR-4, ABF, or the like. However, anyother suitable substrate, such as a silicon interposer, a siliconsubstrate, organic substrate, a ceramic substrate, or the like, mayalternatively be utilized, and all such redistributive substrates thatprovide support and connectivity to the first external contacts 503 arefully intended to be included within the scope of the embodiments.

By utilizing the fill material 173 to fill the opening 171, anadditional layer of protection is provided to the optical path betweenthe optical fiber 901 and the grating coupler 157. In particular, withthe presence of the fill material 173 during processes such as theplanarization process (described above with respect to FIG. 2 , debrisfrom the process is prevented from entering the opening 171 andinterfering with the passage of the optical signals. Further, sensitivestructures such as the grating couplers 157 are further protected fromsuch processes through the presence of the fill material 173, therebypreventing undesired defects from occurring and increasing the overallyield of the manufacturing process.

Further, by packaging the first integrated photonic circuit 105 asdescribed the first photonic integrated circuit 105 can be modularizedin a stand alone package that can achieve good die to die bandwidths byreducing the pitches of the redistribution structures, the TIVs 107, andthe external contacts 164. As such, the stand alone package can bequickly installed as desired with other packages or even co-packagedwith other packages. As such, the first photonic integrated circuit 105may be used and incorporated in a wide variety of uses with a minimum orre-design.

FIGS. 10A-10B illustrate another embodiment in which the first photonicintegrated circuit 105, instead of receiving and/or transmitting lightto an optical fiber 901 located over the top surface, instead receivesand/or transmits light to an optical fiber 901 located along a side ofthe first photonic integrated circuit 105 (see FIG. 16 ), with FIG. 10Billustrating a close-up view with more detail of the dashed box labeled1000 in FIG. 10A. In this embodiment, the TIVs 107 are formed over thefirst carrier substrate 101 and the first photonic integrated circuit105 is placed onto the first carrier substrate 101 as described abovewith respect to FIG. 1A. For example, the TIVs 107 may be formed using aphotoresist patterning and plating process, and the first photonicintegrated circuit 105 is placed using a pick-and-place process.However, any suitable method of formation or placement may be utilized.

Additionally, in this embodiment the first photonic integrated circuit105 may be formed without the opening 171. As such, the fill material173 is formed over the substrate 152, but does not extend into thestructure. Additionally, without the removal of the materials for theopening 171 (e.g., the materials of the fill material 173, theprotection layer 165, the passivation film 163, the redistributionstructure 161, and the dielectric layer 159), the material remainspresent to protect the underlying structures during subsequentprocessing such as chemical mechanical polishing.

Additionally in this embodiment, the waveguide 154 is modified in orderto accept optical signals from a subsequently formed second waveguide1101. In particular, in this embodiment the material of the waveguide154 (e.g., silicon) is formed using, for example, using aphotolithographic masking and etching process and is formed as a taperedwaveguide in order to accept optical signals that are received at anangle instead of being received perpendicular to the waveguide 154.However, any suitable method of forming the waveguide 154 to acceptthese signals may be utilized.

FIG. 10A additionally illustrates the placement of a first semiconductordie 1001 and a second semiconductor die 1003 onto the first carriersubstrate 101 along with the first photonic integrated circuit 105. Inan embodiment the first semiconductor die 1001 and the secondsemiconductor die 1003 are designed to work cooperatively with the firstelectronic integrated circuit 605 and the first photonic integratedcircuit 105 to perform a desired function, and may be, for example,logic dies, memory dies, ASIC dies, or the like.

For example, in embodiments in which one or more of the firstsemiconductor die 1001 and the second semiconductor die 1003 are logicdevices, the first semiconductor die 1001 and the second semiconductordie 1003 may be devices such as central processing units (CPU), graphicsprocessing unit (GPU), system-on-a-chip (SoC) devices, applicationprocessor (AP) devices, microcontrollers, or the like. Additionally, inembodiments in which one or more of the first semiconductor die 1001 andthe second semiconductor die 1003 are memory devices, the firstsemiconductor die 1001 and the second semiconductor die 1003 may be,e.g., a dynamic random access memory (DRAM) die, static random accessmemory (SRAM) die, hybrid memory cube (HMC) device, high bandwidthmemory (HBM) device, or the like. However, any suitable functionalities,defined by any suitable structures, are fully intended to be includedwithin the scope of the embodiments.

In an embodiment both of the first semiconductor die 1001 and the secondsemiconductor die 1003 may further comprise die contact pads 1002, a diepassivation layer 1004, a die protection layer 1005, and die externalcontacts 1006. In an embodiment the die contact pads 1002, the diepassivation layer 1004, the die protection layer 1005, and the dieexternal contacts 1006 may be similar to the contact pads 162, thepassivation film 163, the protection layer 165, and the external contact164, described above with respect to FIG. 1A. However, any suitablestructures may be utilized.

FIG. 10A also illustrates an encapsulation of the TIVs 107, the firstphotonic integrated circuit 105, the first semiconductor die 1001, andthe second semiconductor die 1003. In an embodiment the encapsulationmay be performed as described above with respect to FIGS. 1A and 2 . Forexample, the encapsulant 109 is placed around the TIVs 107, the firstphotonic integrated circuit 105, the first semiconductor die 1001, andthe second semiconductor die 1003, and the encapsulant 109 may beplanarized in order to remove excess portions and expose the TIVs 107,the first photonic integrated circuit 105, the first semiconductor die1001, and the second semiconductor die 1003. However, any suitablematerials and methods may be utilized.

FIG. 10A additionally illustrates that, once the encapsulant 109 hasbeen placed and the chemical mechanical polishing process has beenperformed, a second opening 1007 may be formed as a window extendingfrom a side of the first photonic integrated circuit 105. However,because the planarization process for the encapsulation has alreadyoccurred, the chemical mechanical polishing process can no longer damagestructures within the second opening 1007 and debris from theplanarization process cannot enter into the second opening 1007.

In an embodiment the formation of the second opening 1007 may beperformed using a photolithographic masking and etching process. Forexample, in an embodiment a photoresist is placed over the structure,imaged with a patterned energy source, and developed. Once thephotoresist is in place as a mask, one or more etching processes areutilized to etch through the desired materials and form the secondopening 1007.

Looking at FIG. 10B, in an embodiment the second opening 1007 is formedto extend into the first photonic integrated circuit 105 to a seconddepth D₂ of between about 13.5 μm and about 17.5 μm. Additionally, thesecond opening 1007 may be formed to extend inwards from a sidewall ofthe first photonic integrated circuit 105 to a first distance Dis₁ thatis sufficient to form the second opening 1007 over the waveguides 154within the first photonic integrated circuit 105, such as the firstdistance Dis₁ being between about 100 μm and about 2.5 mm. However, anysuitable dimensions may be utilized.

Additionally, during the formation of the second opening 1007, a portionof the encapsulant 109 may be removed and recessed from the firstphotonic integrated circuit 105. In an embodiment the encapsulant 109may be recessed a third distance D₃ of between about 5 μm and about 20μm below the surface of the second opening 1007. However, any suitabledimension may be used.

FIGS. 11A-11B illustrate formation of a second waveguide 1101 within thesecond opening 1007, with FIG. 11B illustrating a close up and moredetailed view of the dashed box labeled 1100 in FIG. 11A. In anembodiment the second waveguide 1101 is utilized in order to guideoptical signals from the optical fiber 901 (illustrated in thisembodiment in FIG. 16 below) to the waveguides 154 already within thefirst photonic integrated circuit 105. By using the second waveguide1101 which is formed after the encapsulation process, the waveguides 154remain protected and less likely to suffer defects during themanufacturing process.

To initiate the formation of the second waveguide 1101, the recessing ofthe encapsulant 109 is filled with a dielectric fill material 1103. Inan embodiment the dielectric fill material 1103 may be a material suchas polybenzoxazole (PBO), although any suitable material, such aspolyimide or a polyimide derivative, may be utilized. The firstdielectric layer 203 may be placed using, e.g., a spin-coating processto fill the second opening 1007. Once in place, the dielectric fillmaterial 1103 may be recessed using, e.g., a wet or dry etching process.

Once the dielectric fill material 1103 is in place, the second waveguide1101 is formed. In an embodiment the second waveguide 1101 may be anytype of waveguide, such as a planar waveguide or a channel waveguide,and may comprise two different materials, a core material and a claddingmaterial, in which the core material has a refractive index higher thanthe cladding material.

In an embodiment the second waveguide 1101 may be a polymer waveguideand the core material and the cladding material comprise a combinationof polymer materials, such as poly(methylmethacrylate) (PMMA),polystyrene (PS), polycarbonate, polyurethane, benzocyclo butane,perfluorovinyl ether cyclopolymer, tetrafluoroethylene, perfluorovinylether copolymer, silicone, fluorinated poly(arylene ether sulfide,poly(pentafluorostyrene), fluorinated dendrimers, fluorinatedhyperbranched polymers, or the like. In another embodiment, the corematerial and the cladding material may comprise deuterated andhalogenrate polyacrylates, fluorinated polyimides, perfluorocyclobutylaryl ether polymers, nonlinear optical polymers, or the like. In yetanother embodiment, the core material and the cladding material maycomprise silicon or silicon dioxide, to utilize the index of refractionbetween the materials to confine and constrain the path of the opticalsignals through the second waveguide 1101.

The core material and the cladding material of the second waveguide 1101may be formed, e.g., by initially placing each layer or combination oflayers within the second opening 1007 using a process such as spincoating, doctor blading, extrusion, lamination, or the like. As eachlayer is formed, the layer may be patterned and shaped in order tocontrol and direct the optical signals to and from the waveguide 154located further within the first photonic integrated circuit 105. Forexample, as each layer of material of the second waveguide 1101 isformed, a series of one or more etches such as wet etches or dry etches,may be used to shape the layers of material as desired. However anysuitable methods may be utilized.

FIGS. 11A-11B additionally illustrates that, once the second waveguide1101 has been formed, the first redistribution structure 201 may beformed over the encapsulant 109 and the first photonic integratedcircuit 105. In an embodiment the first redistribution structure 201 maybe formed as described above with respect to FIG. 2 , such as by placingand patterning dielectric layers, and then forming conductive lines overand through the dielectric layers. However, any suitable materials andmethods may be utilized.

However, because this embodiment utilizes a second waveguide 1101 whichallows for a connection of the optical fiber 901 from a side of thefirst photonic integrated circuit 105, the conductive layers of thefirst redistribution structure 201 may additionally be formed over thewaveguide 154 and the second waveguide 1101. As such, a larger area formanufacture may be achieved.

FIG. 12 illustrates a transfer of the structure to the second carriersubstrate 301 using the second adhesive layer 303. In an embodiment thetransfer may be performed as described above with respect to FIG. 3 ,such as by attaching the first redistribution structure 201 to thesecond adhesive layer 303, removing the first carrier substrate 101, andthen thinning the encapsulant, the TIVs 107, the first photonicintegrated circuit 105, the first semiconductor die 1001, and the secondsemiconductor die 1003. However, any suitable methods may be utilized.

FIG. 13 illustrates a formation of the second redistribution structure401 in electrical connection with the TIVs 107. In an embodiment thesecond redistribution structure 401 may be formed as described abovewith respect to FIG. 4 , such as by placing and patterning dielectriclayers, and then forming conductive lines over and through thedielectric layers, and repeating this process as often as desired.However, any suitable materials and methods may be utilized.

FIG. 14 illustrates formation of the UBMs 501 and formation of the firstexternal contacts 503. In an embodiment the UBMs 501 and the firstexternal contacts 503 may be formed as described above with respect toFIG. 5 . For example, the UBMs 501 may be formed through one of thedielectric layers of the second redistribution structure 401, the firstexternal contacts 503 are formed and/or placed over the UBMs 501, and areflow process may be performed. However, any suitable methods andmaterials may be utilized.

FIG. 15 illustrates a placement of the structure on the ring structure601, a removal of the second carrier substrate 301, a placement of thesecond external connectors 607, and the placement of the firstelectronic integrated circuit 605 using, e.g., a pick and place process.

FIG. 15 additionally illustrates the placement of a third semiconductordie 1501. In an embodiment the third semiconductor die 1501 may besimilar to the first semiconductor die 1001 and/or the secondsemiconductor die 1003 (e.g., may be a logic die, a memory die, or thelike) and may be placed in a similar fashion (e.g., through a pick andplace process). However, any suitable functionality and any suitablemethod of placement may be utilized.

FIG. 16 illustrates a bonding of the first electronic integrated circuit605 and the third semiconductor die 1501 to the first redistributionstructure 201. In an embodiment the bonding may be performed asdescribed above with respect to FIG. 7 , such as by performing a reflowprocess. However, any suitable method of bonding may be utilized.

FIG. 16 additionally illustrates a placement of the first underfill 701between the first redistribution structure 201 and the first electronicintegrated circuit 605 and the third semiconductor die 1501, and asingulation of the structure such that the second waveguide 1101 isplanar with the encapsulant 109 and the first redistribution structure201. In an embodiment the placement of the first underfill 701 and thesingulation process may be performed as described above with respect toFIGS. 7 and 8 . However, any suitable methods and materials may beutilized.

Finally, FIG. 16 illustrates a placement of the optical fiber 901 inoptical connection with the second waveguide 1101. In an embodiment theoptical fiber 901 routes optical signals into the second waveguide 1101,which receives the optical signals and guides them into the firstphotonic integrated circuit 105 and towards the waveguide 154. By usingthe second waveguide 1101, the waveguide 154 can remain protected andfewer defects can occur during the manufacturing process.

FIG. 17 illustrates yet another embodiment in which the structures ofthe first photonic integrated circuit 105 (as described above withrespect to FIGS. 1A-1B) are protected using the fill material and theformation of the second waveguide 1101. In this embodiment, however, thefirst electronic integrated circuit 605 is embedded within theencapsulant 109 along with the first photonic integrated circuit 105. Inthis embodiment the TIVs 107 are not formed over the first carriersubstrate 101, and both the first photonic integrated circuit 105 andthe first electronic integrated circuit 605 are formed, singulated, andplaced on to the first carrier substrate 101 and the first adhesivelayer 103 using, e.g., a pick and place process.

Additionally, FIG. 17 also illustrates placement of the encapsulant 109around the first photonic integrated circuit 105 and the firstelectronic integrated circuit 605. In an embodiment the encapsulant 109may be placed as described above with respect to FIG. 1A. However, anysuitable material and method may be utilized to encapsulate the firstphotonic integrated circuit 105 and the first electronic integratedcircuit 605.

FIG. 18 illustrates a planarization process to remove excess material ofthe encapsulant 109 and the fill material 173 and to expose the externalcontacts 164 of the first photonic integrated circuit 105 and the EICexternal contact 617 of the first electronic integrated circuit 605. Inan embodiment the planarization process may be a chemical mechanicalpolishing process, although any suitable planarization process, such asmechanical grinding or even a series of one or more etching processes,may be utilized.

FIG. 18 also illustrates a deposition and patterning of a first hardmask layer 1801 over the encapsulant 109, the first photonic integratedcircuit 105 and the first electronic integrated circuit 605. In anembodiment the first hard mask layer 1801 may be a material such astitanium, tantalum, combinations of these, or the like, using adeposition process such as chemical vapor deposition, physical vapordeposition, atomic layer deposition, combinations of these, or the like.However, any suitable materials and methods of deposition may beutilized.

Once the first hard mask layer 1801 has been deposited, the first hardmask layer 1801 may be patterned in order to expose a portion of thefill material 173 over the grating coupler 157 for removal. In anembodiment the first hard mask layer 1801 may be patterned using aphotolithographic masking and etching process in order to form opening171 (as shown in FIG. 1B) over the grating coupler 157. However, anysuitable method may be used to pattern the first hard mask layer 1801.

In an embodiment the first hard mask layer 1801 may be patterned to havean opening with a third width W₃ that is sufficient for the subsequentremoval of the underlying fill material 173 as well as formation of thesecond waveguide 1101 (not illustrated in FIG. 18 but illustrated anddescribed below with respect to FIG. 21 ). As such, in some embodimentsthe third width W₃ may be between about 100 μm and about 2.5 mm,although any suitable dimensions may be utilized.

FIG. 19 illustrates that, once the first hard mask layer 1801 haspatterned, that portion of the fill material 173 that is exposed may beremoved to expose the grating coupler 157 and the waveguide 154 and forma third opening 1901. In an embodiment the removal may be performedusing an ashing process in the presence of oxygen. In such a process,the temperature of the fill material 173 is increased until the exposedportions, in contact with the oxygen ambient, undergo a decompositionprocess and are removed. However, any suitable process, such as ananisotropic etching process, may be used to remove the exposed portionsof the fill material 173 and expose the grating coupler 157. In anembodiment the third opening 1901 may be formed with the third width W₃and a third depth D₃ of between about 13.5 μm and about 31 μm. However,any suitable dimensions may be utilized.

FIG. 20 illustrates an optional trimming process that may be utilized inorder to recess the fill material 173 away from the grating coupler 157.In an embodiment the first hard mask layer 1801 may be removed using,e.g., a wet or dry etching process. However, any suitable process may beused to remove the first hard mask layer 1801.

Once the first hard mask layer 1801 has been removed, a separatephotolithographic masking and etching process may be utilized in orderto recess the material of the fill material 173. By recessing thematerial, the third opening 1901 may be extended to have a fourth widthW₄ of between about 100 μm and about 2.5 mm. However, any suitabledimension may be utilized.

FIG. 21 illustrates that once the trimming process has been performed,the second waveguide 1101 may be formed within the first photonicintegrated circuit 105. In an embodiment the second waveguide 1101 maybe formed as described above with respect to FIG. 11 . For example, aseries of polymer materials are deposited and patterned into the thirdopening 1901. Once deposited the materials can be planarized. However,any suitable method of forming the second waveguide 1101 may beutilized.

FIG. 21 also illustrates that once the second waveguide 1101 has beenformed, the first redistribution structure 201 may be formed in order tointerconnect the first photonic integrated circuit 105 and the firstelectronic integrated circuit 605. In an embodiment the firstredistribution structure 201 may be formed as described above withrespect to FIG. 2 . For example, a series of dielectric and conductivematerials are alternatingly deposited and/or patterned to form the firstredistribution structure 201. However, any suitable methods andmaterials may be utilized.

FIG. 21 additionally illustrates a formation of the UBMs 501 and thefirst external contacts 503. In an embodiment the UBMs 501 and the firstexternal contacts 503 may be formed as described above with respect toFIG. 5 . For example, the UBMs 501 may be formed through one of thedielectric layers of the first redistribution structure 201, the firstexternal contacts 503 are formed and/or placed over the UBMs 501, and areflow process may be performed. However, any suitable methods andmaterials may be utilized.

Finally, FIG. 21 illustrates a placement of the optical fiber 901 overthe second waveguide 1101. In an embodiment the optical fiber 901 may beplaced within a trench formed within the first redistribution structure201 and positioned in order to send and receive optical signals to thesecond waveguide 1101. However, any suitable placement may be utilized.

By utilizing the fill material 173 to protect the underlying structuresduring the planarization process of the encapsulant 109, no debris fromthe planarization process can get embedded and interfere with thesubsequent processing or operation of the first photonic integratedcircuit 105. Further, the material of the fill material 173 is presentto protect the underlying structures during the planarization process,leading to less damage and fewer defects.

FIG. 22 illustrates yet another embodiment in which the modularizedembodiment illustrated in FIGS. 1A-9 is, instead fully integrated into adevice with the first semiconductor die 1001, the second semiconductordie 1003, the third semiconductor die 1501, and a fourth semiconductordevice 2201 (which may be similar to the first semiconductor die 1001).In this embodiment the first photonic integrated device 105 as describedabove with respect to FIGS. 1A-1B is encapsulated with the firstsemiconductor die 1001 and the second semiconductor die 1003, and thenthe first photonic integrated circuit 105 is processed as describedabove with respect to FIG. 1B. Once encapsulated, the firstredistribution structure 201 and the second redistribution structure 401are formed, and the first electronic integrated circuit 605 and thethird semiconductor die 1501 are bonded. Additionally, the fourthsemiconductor device 2201 is bonded to the first redistributionstructure 201 in a similar fashion as the third semiconductor die 1501.

By integrating the first photonic integrated circuit 105 with the firstsemiconductor die 1001, the second semiconductor die 1003, the thirdsemiconductor die 1501 and the fourth semiconductor device 2201, a fullyintegrated device with all of the desired functionality co-packaged canbe obtained that is easily scalable to any desired bandwidth. In oneparticular embodiment, the first semiconductor die 1001 and the secondsemiconductor die 1003 may be both be logic chips (e.g., LSIs), thethird semiconductor die 1501 may be an ASIC device, and the fourthsemiconductor device 2201 may be a memory device such as a highbandwidth memory. However, any suitable combination of devices may beutilized in order to form a fully incorporated device with the firstphotonic integrated circuit 105.

By utilizing the embodiments described herein, a cost effective siliconphotonic device can be achieved which utilizes homogenous protectionlayers such as the fill material 173 and/or secondary waveguides (e.g.,the second waveguide 1101) without the use of through silicon vias inthe first photonic integrated circuit 105. By using these structures,other structures, such as grating couplers 157 or waveguides 154 canremain protected from damage and contamination during certain in-situmanufacturing processes such as chemical mechanical polishing processes.By utilizing this protection, the overall fabrication process includingthe edge coupler to grating coupler fiber assembly can be eased.

In accordance with an embodiment, a method of manufacturing asemiconductor device includes; removing a portion of a first photonicintegrated circuit device to form an opening as an optical pathway to agrating coupler within the first photonic integrated circuit device;filling the opening with a fill material; and forming a firstredistribution layer over the fill material. In an embodiment the methodfurther includes: forming a through via on a carrier substrate; placingthe first photonic integrated circuit device adjacent to the through viaon the carrier substrate; and encapsulanting the through via and thefirst photonic integrated circuit device with an encapsulant, whereinthe forming the first redistribution layer forms the firstredistribution layer over the fill material. In an embodiment the methodfurther includes, prior to the forming the first redistribution layer,planarizing the fill material, the through via, and the encapsulant. Inan embodiment the method further includes forming a secondredistribution layer on an opposite side of the first photonicintegrated circuit device from the first redistribution layer. In anembodiment the method further includes attaching a first electronicintegrated circuit to the first redistribution layer. In an embodimentthe fill material comprises polyimide.

In accordance with an embodiment, a semiconductor device includes: afirst photonic integrated circuit, the first photonic integrated circuitincluding: a semiconductor substrate; a waveguide formed within thesemiconductor substrate; a grating coupler formed within thesemiconductor substrate; a fill material overlying the grating coupler;and external contacts planar with the fill material; and aredistribution layer overlying the fill material and the externalcontacts. In an embodiment the semiconductor device further includes anencapsulant surrounding the first photonic integrated circuit. In anembodiment the semiconductor device further includes through viasextending from a first side of the encapsulant to a second side of theencapsulant. In an embodiment the semiconductor device further includesan electronic integrated circuit bonded to the redistribution layer. Inan embodiment the semiconductor device further includes a firstsemiconductor die located within the encapsulant. In an embodiment thesemiconductor device further includes an electronic integrated circuitbonded to the redistribution layer. In an embodiment the semiconductordevice further includes an optical fiber located over the redistributionlayer. In an embodiment the fill material is polyimide.

In accordance with yet another embodiment, a semiconductor deviceincludes: a photonic integrated circuit including: a first waveguideover a substrate; and a second waveguide at least partially over thefirst waveguide; and a redistribution layer overlying the secondwaveguide, the redistribution layer having a surface that is co-planarwith a surface of the second waveguide. In an embodiment, thesemiconductor device further includes: an encapsulant encapsulating thephotonic integrated circuit; and through vias extending through theencapsulant. In an embodiment the semiconductor device further includesa first semiconductor die within the encapsulant. In an embodiment thesemiconductor device further includes a second redistribution layerlocated on an opposite side of the first semiconductor die than theredistribution layer. In an embodiment the first waveguide is a siliconwaveguide and the second waveguide is a polymer waveguide. In anembodiment the semiconductor device further includes: a dielectricmaterial located between the second waveguide and the encapsulant; andan optical fiber located adjacent to the second waveguide.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A method of manufacturing an optical device, themethod comprising: patterning a first material to form channels as partof a grating coupler; depositing a dielectric material over the gratingcoupler; forming an opening at least partially through the dielectricmaterial over the grating coupler; filling the opening with a fillmaterial; and forming a first redistribution layer over the fillmaterial.
 2. The method of claim 1, further comprising forming a throughvia on a carrier substrate, wherein the forming the first redistributionlayer forms the first redistribution layer over the through via.
 3. Themethod of claim 2, further comprising forming a second redistributionlayer on an opposite side of the grating coupler from the firstredistribution layer.
 4. The method of claim 1, wherein the forming theopening forms the opening to have a first width adjacent to the gratingcoupler of between about 20 μm and about 30 μm.
 5. The method of claim4, wherein the forming the opening forms the opening to have a secondwidth of between about 30 μm and about 40 μm.
 6. The method of claim 1,further comprising attaching a first electronic integrated circuit tothe first redistribution layer.
 7. A method of manufacturing asemiconductor device, the method comprising: forming a photonicintegrated circuit with a grating coupler adjacent to a first side, thegrating coupler comprising a plurality of channels; depositing one ormore dielectric materials over the grating coupler; replacing at least aportion of the one or more dielectric materials with a fill material;encapsulating the photonic integrated circuit with a through via with anencapsulant, wherein the encapsulant comprises a single continuousmaterial throughout the encapsulant; and planarizing the encapsulantwith the fill material.
 8. The method of claim 7, further comprisingplacing an optical fiber over the grating coupler.
 9. The method ofclaim 7, further comprising: forming a first redistribution layer on afirst side of the through via; and forming a second redistribution layeron a second side of the through via opposite the first side.
 10. Themethod of claim 9, further comprising bonding an electronic integratedcircuit to the first redistribution layer.
 11. The method of claim 7,wherein the encapsulating the photonic integrated circuit furtherencapsulates an electronic integrated circuit.
 12. The method of claim7, wherein the fill material comprises an epoxy.
 13. The method of claim7, wherein the fill material comprises a siloxane.
 14. The method ofclaim 7, further comprising forming the through vias, the forming thethrough vias comprising: forming a seed layer on a substrate; placingand patterning a photoresist over the seed layer; plating a conductivematerial onto the seed layer through the photoresist; removing thephotoresist; and removing a portion of the seed layer.
 15. A method ofmanufacturing an optical device, the method comprising: forming a firstsubstrate, the first substrate comprising: an encapsulant, wherein theencapsulant comprises a single continuous material throughout theencapsulant; a through via extending from a first side of theencapsulant to a second side of the encapsulant; a photonic integratedcircuit with a grating coupler; and a fill material planar with each ofthe encapsulant, the through via, and an external connector of thephotonic integrated circuit; forming a first redistribution layer on afirst side of the first substrate; and forming a second redistributionlayer on a second side of the first substrate opposite the first side.16. The method of claim 15, bonding a first electronic integratedcircuit to the first redistribution layer.
 17. The method of claim 15,wherein the first substrate further comprises an electronic integratedcircuit.
 18. The method of claim 15, wherein the fill material has afirst width of between about 20 μm and about 30 μm.
 19. The method ofclaim 18, wherein the fill material has a second width of between about30 μm and about 40 μm.
 20. The method of claim 15, wherein the fillmaterial comprises siloxane.